This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-043643, filed Feb. 20, 2001; and No. 2002-038244, filed Feb. 15, 2002, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More specifically, the present invention relates to a data writing method for a nonvolatile semiconductor memory device capable of decreasing the disturbance of the data due to capacitance coupling even if the distance between adjacent memory cells becomes narrow, and the nonvolatile semiconductor memory device.
2. Description of the Related Art
A nonvolatile semiconductor memory to read the information, has been developed, in such a manner that an electric charge, which is injected from a channel to an charge accumulation layer through a tunnel insulation film by a tunneling current, is used as information storage of a digital bit and the conductance change of MOSFET in accordance with its electric charge amount is measured. However, according to a constitution of a conventional nonvolatile semiconductor memory and a conventional writing method, in concurrence with high accumulation of a memory cell, the capacitance coupling between the charge accumulation layers of the memory cells is increased, so that this involves a problem such that the data of the adjacent memory cells is disturbed dependent on an order of writing. First, a problem in a conventional example will be explained with reference to FIGS. 37 to 43.
FIG. 38A and FIG. 38B illustrate circuit diagrams of a cell block of a conventional NAND type and a cell block of a conventional AND type EEPROM.
In FIG. 38A and FIG. 38B, reference numerals MO to M15 and M0xe2x80x2 to M15xe2x80x2 denote memory cells and reference numerals 49 and 49xe2x80x2 respectively denote one memory cell block to be formed, for example, by a NAND type block and an AND type block. A plurality of data selection lines (WL0 to WL15) is connected to one memory cell block 49, 49xe2x80x2. Alternatively, memory cell block selection lines SSL and GSL are connected to the memory cell block 49. Further, reference numerals BL1 and BL2 denote data transfer lines and they are arranged in a direction mutually orthogonal to the data selection line (not shown). Each memory cell in the memory cell block 49 is formed at an intersecting point of the data transfer line and the data selection line. In each memory cell, it is possible to data store and data read, independently. In this case, assume a memory cell is a transistor having, for example, a charge accumulation layer and representing data by the electric charge amount of its charge accumulation layer. These plural memory cell blocks 49 are formed in a direction of the data transfer line and in a direction of the data selection line to form a memory cell array 1.
FIG. 39 illustrates a layout example of a memory cell array 1 and a sense amplifier 46 according to a conventional example including a sense amplifier circuit. In FIG. 39, in order to make the drawing understandable, the data selection lines WL0 to WL15 and the block selection lines SSL and GSL are omitted.
In FIG. 39, reference numerals BL1x, BL2x (x=a, b, c . . . k) denote data transfer lines. The memory cell blocks 49 and 49xe2x80x2 shown in FIG. 38 are connected to the data transfer lines, respectively and the data transfer lines are connected to one sense amplifier x via Q1x and Q2x. The subscripts such as a, b, . . . k are indices which are attached conveniently for representing plural lines of memory cell layouts and a total number of the indices may be any number if it is a plural number. In other words, the sense amplifier needs a transistor larger than one memory cell, so that one sense amplifier 46 is shared by a plurality of data transfer lines so that an area occupied by the sense amplifier is contracted. Further, the sense amplifier 46 serves to read the data of the memory cell and it doubles with a data register, which temporally keeps data to be written in the memory cell. Further, this sense amplifier 46 is commonly connected to data lines I/O and I/OB for connecting writing and the reading data to a data input/output buffer 45, respectively. Following a general rule, a direction along the data selection line is referred to as a row and a direction along the data transfer line is referred to as a column below.
In the case of writing data in the memory cell M1xe2x80x2 of the memory cell block 49xe2x80x2 in the conventional circuit of FIG. 38, the data transfer line BL2 connected to the sense amplifiers is biased, for example, in such a manner that the output voltage of the data register takes a voltage value in accordance with the written data. At the same time, a program voltage Vpgm having a potential difference which is sufficiently larger than the potential of the data transfer line which writes the data is pulsed in time to a sufficient extent for injecting a carrier to be applied to the data selection line WL1 in such a manner that the sufficiently high voltage is applied so that the current flows through the tunnel insulation film of a nonvolatile memory element of the memory cell. In this case, it is necessary that the data of M1xe2x80x2 should not written in the memory cell block 49 adjacent to the memory cell block 49xe2x80x2. Further, it is also necessary that the data of M1xe2x80x2 should not written in the memory cell M0xe2x80x2 adjacent to M1xe2x80x2. Alternatively, according to the conventional example, these memory cells M0xe2x80x2, M1xe2x80x2 and M1 are connected to one sense amplifier 46, so that it is not possible to write arbitrary data in a plurality of memory cells connected to one sense amplifier.
Next, FIG. 40 shows a writing sequence according to the conventional example, in which a problem occurs.
FIG. 40 illustrates a flowchart for independently writing data, for example, in the memory cells M1 and M1xe2x80x2 belonging to two adjacent columns. The present example is formed on the same well. In the present example, it is supposed that a flash memory in which the data is entirely deleted. Further, in the present example, it is supposed that an initial state of the memory cell is a state that all data are xe2x80x9c11xe2x80x9d, namely, a state that the negative accumulated electric charge in the charge accumulation layer is most decreased. In a constitution of the conventional example, according to a procedure for writing data in a cell at a first column connected to BL1, at first, the written data is latched in a data register of the sense amplifier 46 through an I/O and an I/OB and then, a step (SE120) is performed to determine whether or not the data are sufficiently written in all memory cells at the first column in such a manner that the written data at the first column is written, the data at the first column is read and a determination result of a threshold voltage of the written memory cell is stored in the data register of the sense amplifier 46. Hereby, it is possible to form, for example, a threshold voltage distribution of the memory cell M1xe2x80x2 as shown by a broken line in FIG. 41. According to the custom, it is assumed that four threshold distributions correspond to values of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d in sequence from a distribution in which the threshold voltage is lower.
Next, the arbitrary data of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d is written in the adjacent memory cell M1 in a row direction (SE121). Hereby, a negative electric charge of the charge accumulation layer of M1 is increased in accordance with the value of each data. In this case, if the negative electric charge of the charge accumulation layer of M1 is increased, its voltage rises. In this case, the charge accumulation layer lies in an electrically floating state, so that a voltage of the charge accumulation layer of M1xe2x80x2 is increased by the capacitance coupling between the charge accumulation layer of M1xe2x80x2 and the charge accumulation layer of M1 as the negative electric charge amount of M1 is increased. This threshold voltage is most increased in the case that the data of M1 adjacent to M1xe2x80x2 is xe2x80x9c01xe2x80x9d. In the case that it is xe2x80x9c11xe2x80x9d, the threshold voltage is not changed. Since the data of M1 can take an arbitrary value, xe2x80x9cincrementation of the distribution width of the threshold voltagexe2x80x9d occurs as shown by a solid line in FIG. 41. This increasing amount is not capable of being controlled while writing the data in the SE120 according to the conventional example.
Accordingly, if a sequence (SE122) for reading the data of M1xe2x80x2 is performed after that, the above described xe2x80x9cincrementation of the distribution width of the threshold voltagexe2x80x9d reduces the margin between a reference threshold voltage for reading and a written threshold voltage is decreased. As a result, for example, a probability of mal-reading the data of xe2x80x9c10xe2x80x9d as xe2x80x9c00xe2x80x9d and a probability of mal-reading the data of xe2x80x9c00xe2x80x9d as xe2x80x9c01xe2x80x9d are increased.
On the other hand, conventionally, the same problem occurs also in a memory cell belonging to an adjacent row. FIG. 42 shows a flowchart for writing the data independently in two adjacent rows. It is supposed that an initial state of the memory cell is a state that all data are xe2x80x9c11xe2x80x9d, namely, a state that the negative accumulated electric charge in the charge accumulation layer is most decreased.
At first, the arbitrary data of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d is written in the memory cell M1xe2x80x2 connected to WL1 (SE123). Hereby, for example, it is possible to form a threshold voltage distribution of the memory cell M1xe2x80x2. Next, the arbitrary data of xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d is written in the memory cell M0xe2x80x2 adjacent in a column direction. Hereby, a negative electric charge of the charge accumulation layer of M0xe2x80x2 is increased in accordance with the value of each data. In this case, if the negative electric charge of the charge accumulation layer of M0xe2x80x2 is increased, its voltage rises. The charge accumulation layer lies in an electrically floating state, so that a voltage of the charge accumulation layer of M1xe2x80x2 is increased by the capacitance coupling between the charge accumulation layer of M1xe2x80x2 and the charge accumulation layer of M0xe2x80x2 as the negative electric charge amount of M0xe2x80x2 is increased. This threshold voltage is most increased in the case that the data of M0xe2x80x2 adjacent to M1xe2x80x2 is xe2x80x9cO1xe2x80x9d. In the case that it is xe2x80x9c11xe2x80x9d, the threshold voltage is not changed. Since the data of M0xe2x80x2 can take an arbitrary value, xe2x80x9cincrementation of the distribution width of the threshold voltagexe2x80x9d occurs as shown by a solid line in FIG. 43. The M0xe2x80x2 and M1xe2x80x2 are connected to one sense amplifier 46, so that this increasing amount is not capable of being controlled while writing the data in the SE123 according to the conventional example.
Accordingly, if a sequence (SE125) for reading the data of M1xe2x80x2 after that, by the above described incrementation of the threshold voltage, the difference between the reading threshold voltage and the writing threshold voltage is decreased. As a result, for example, a probability of mal-reading the data of xe2x80x9c10xe2x80x9d as xe2x80x9c00xe2x80x9d and a probability of mal-reading the data of xe2x80x9c00xe2x80x9d as xe2x80x9c01xe2x80x9d are increased and the data destruction such that the data of xe2x80x9c00xe2x80x9d becomes the data of xe2x80x9c01xe2x80x9d and the data of xe2x80x9c10xe2x80x9d becomes the data of xe2x80x9c00xe2x80x9d.
Alternatively, it is obvious that a problem in the memory cell belonging to the adjacent row also occurs in a constitution such that one sense amplifier is connected to one data transfer line.
Further, in order to prevent misreading of the data, it is needed that a whole threshold voltage distribution of a cell is enlarged to a higher threshold voltage. In this case, a data retention characteristic of a higher threshold voltage is worsened compared to the data retention characteristic of a lower threshold voltage due to a self electric field of the accumulated electric charge, so that it becomes difficult to obtain a sufficient data retention characteristic.
Further, in a memory cell block of the NAND type formed in such a manner that a memory cell is connected in series as shown in FIG. 38A, it is necessary for a memory cell connected in series to a cell to read the data to apply a voltage higher than the highest value of the whole threshold voltage distribution to a gate. Therefore, by repeating the reading operation, a negative electric charge is injected in the charge accumulation layer and a threshold voltage rises, so that the threshold voltage of xe2x80x9c11xe2x80x9d is increased and this accounts for the data destruction and the misreading of the data.
As described above, according to a conventionally constituted nonvolatile semiconductor memory, the data is changed by the capacitance coupling if the data is written in the adjacent memory cell.
A data writing method for a semiconductor memory device according to a first aspect of the present invention comprises: writing data into the first memory cell; writing data into the second memory cell adjoining the first memory cell following writing the data into the first memory cell; verifying the data of the first memory cell after writing the data into the second memory cell; and rewriting the data into the first memory cell when insufficiency of the data of the first memory cell as a result of verifying the data of the first memory cell.
A data writing method for a semiconductor memory device according to a second aspect of the present comprises: writing data into the first memory cell; writing data into the second memory cell connected in series or in parallel to the first memory cell following writing the data into the first memory cell; verifying the data of the first memory cell after writing the data into the second memory cell; and rewriting the data into the first memory cell when insufficiency of the data of the first memory cell as a result of verifying the data of the first memory cell.
A semiconductor integrated circuit device according to a third aspect of the present invention comprises: a first memory cell block capable of rewriting data, the first memory cell block having at least one first memory cell; a second memory cell block capable of rewriting data, the second memory cell block having at least one second memory cell adjacent to the first memory cell; a first data transfer line, the first data transfer line being electrically connected to the first memory cell block directly or via a selective element to select the first memory cell block; a second data transfer line, the second data transfer line being electrically connected to the second memory cell block directly or via a selective element to select the second memory cell block; a charge circuit, the charge circuit charging any one of the first data transfer line and the data transfer line; a first data store circuit, the first data store circuit having a stable point in at least two voltages; a second data store circuit, the second data store circuit being electrically connected to the first data store circuit; a third data store circuit, the third data store circuit being electrically connected to the first data store circuit; a charge/discharge circuit, the charge/discharge circuit charging or discharging a first voltage node on the basis of the data held in the third data store circuit; a first connecting circuit, the first connecting circuit electrically connecting the first voltage node to any one of the first and second data transfer lines; a fourth data store circuit, the fourth data store circuit having a stable point in at least two voltages; and a second connecting circuit, the second connecting circuit electrically connecting the fourth data store circuit to the first voltage node.
A semiconductor integrated circuit device according to a fourth aspect of the present invention comprises: a memory cell block capable of rewriting data, the memory cell block having at least two first and second memory cells connected in series or in parallel and adjoin each other; a data transfer line, the transfer line being electrically connected to the memory cell block directly or via a selective element to select the memory cell block; a charge circuit, the charge circuit charging the data transfer line; a first data store circuit, the first data store circuit having a stable point in at least two voltages; a second data store circuit, the second data store circuit being electrically connected to the first data store circuit; a third data store circuit, the third data store circuit being electrically connected to the first data store circuit; a charge/discharge circuit, the charge/discharge circuit charging or discharging a first voltage node on the basis of the data held in the third data store circuit; a first connecting circuit, the first connecting circuit electrically connecting the first voltage node to the data transfer lines; a fourth data store circuit, the fourth data store circuit having a stable point in at least two voltages; and a second connecting circuit, the second connecting circuit electrically connecting the fourth data store circuit to the first voltage node.
A semiconductor integrated circuit device according to a fifth aspect of the present invention comprises: a first memory cell array, the first memory cell array including first and second memory cell blocks capable of rewriting data and having a plurality of memory cells, which are arranged each other in a direction orthogonal to a data transfer line and are connected in series or in parallel, and data selection lines, which are formed in a direction orthogonal to the data transfer line and are connected in parallel in the first and second memory cell blocks; wherein a memory cell of the first memory cell array stores the data of 3 values or more as a logical value; and a second memory cell array, the second memory cell array including third and fourth memory cell blocks capable of rewriting the data and having a plurality of memory cells, which are arranged each other in a direction orthogonal to the data transfer line with respect to the first memory cell array and are connected in series or in parallel and sharing a data selection line with the data selection line of the first memory cell array, wherein a memory cell of the second memory cell array stores the data of 2 values as a logical value.
A semiconductor integrated circuit device according to a sixth aspect of the present invention comprises: a plurality of first memory blocks capable of rewriting data; and a plurality of second memory blocks capable of rewriting data, wherein when the data is erased from the plurality of first memory blocks and the plurality of second memory blocks, the data is written in the plurality of first memory blocks and the data is read from the plurality of second memory blocks as keeping the erasing state, the read data of the plurality of second memory blocks is identical with the read data of the first memory blocks.